EEPROM Testing


Endurance: The number of write/erease cycles an EEPROM can withstand before a memory bit fails

Retention: The length of time an EEPROM can reliably retain data after programming

Industrial Standards:

Beside the outdated MIL – STD cycling test Method 1033 (1977), there are no formal industrial standards for determining techniques for parameters of endurance or retention claims found in data sheets. Claims of different manufacturers of the same product would vary by factors in excess of 10.

At write/erease cycles below 1 million, failure level is low but non- zero. These random failures are below screening procedure threshold. Failure rates increases rapidly above 1 million cycles and these intrinsic failures describes the end of useful life.

Failure Types:

Two basic failure modes occur when EEPROM cells are repeatedly written and ereased: dielectric fails and charge trapping. Dielectric fails are source of random fails and caused by leakage current caused by marginal tunnel oxyde quality. Charge trapping creates intrinsic failures. Small amounts of isolated charge become trapped in imperfections in the tunnel oxide during write/erease cycling. This charge is no longer free to tunnel out of the oxide and creates a barrier to the tunneling of other electrons. Thus, the voltage needed to tunnel in either direction increases or the amount of charge decreases until its no longer possible to distinguish a one from a zero. Also, the trapped electrons shifts the threshold voltage of the cell transistor.

While qualification testing(1 000 000+ cycles) and lot qualification testing(sample tests) ares not focus of this article, common production test screening procedures are presented here:

Pre Bake Test: Multiple cycle r/w (endurance test to screen infant mortality), measurement of programming current, write/erases all cells before retention bake

Data Retention Bake is a high temperatur storage to examine the written data stability of EEPROM units. No electrical stress applied. Usually 96 hours at 150°C or 48 hours at 180°C to accelerate charge loss

Post Bake Test including

  • Test of Floating Gate Transistors threshold voltage to ensure enough threshold voltage margin

    Stress test: application of an elevated voltage (e.g. 10 V for a 5V CMOS device) for a well defined time and a read cycle test

  • Test Setup:

    Particularly for evaluating new EEPROM process technology, it is essential to do multipass probing, i.e. Post Bake Test should test PASS devices of the first test only and skip FAIL devices of the first pass. Wihout multipass probing, endurance and data retention fails cannot be isolated, monitored, wafermapped and analyzed. Thus, process engineering will not have feed back data.

    To prevent excess continuity fails on the second test due to AL oxidation during 96h retention bake, a gas tight LN2 flooded oven is very much recommended.

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